1. Technical Field
The present invention is generally directed to an improved multichip integrated circuit module. More particularly, the present invention relates to a packaging method for electronic integrated circuit chips, particularly very large scale integrated circuit (VLSI) devices, on a substrate also having a polymer encapsulant overlying the chips on the substrate and providing a means for supporting inter chip and intra chip connection conductors. Even more particularly, the present invention relates to a repairable multichip module structure and corresponding repair method; a multichip module structure having high I/O capacity with optimal heat removal through one side and high performance I/O through an opposite side; multichip module structures optimized for speed; multichip module structures having the ability to incorporate an assortment of components of varying thickness and function therein; and multichip modules having an integrated hermetic structure with high I/O count.
2. Description of the Prior Art
Multichip modules are divided into two basic structures. In the most common structure, a miniature circuit board is provided upon which integrated circuits are mounted and electrically connected. The second multichip module structure involves mounting chips on a substrate, and subsequently providing interconnect to the chips by essentially building an interconnecting circuit board over the top of the chips. These two approaches are referred to herein as "chip on board" for the first approach, and "circuit board above chips" for the second approach.
In the "chip on board" approach, the circuit board is typically fabricated using alumina or silicon substrate, with copper or aluminum interconnection metallization. The most frequently used dielectric is polyimide. Silicon dioxide can be used as a dielectric on silicon substrates with certain thermal advantages. There are three primary methods for making connection from the pads of the chips to the miniature circuit board. These are wire bonding, tape automated bonding or tab bonding, and flip chip or solder bump bonding. Each of these approaches, including their advantages and disadvantages, are discussed below.
There are two know prior art approaches for the "circuit board above chips" technique. These approaches are the Semiconductor Thermoplastic Dielectric (STD) process and the High Density Interconnect (HDI) overlay process. In the STD process chips are mounted on a substrate and a thermoplastic dielectric is pressed over the chips at high temperature and pressure such that it fills the gaps between the chips and leaves a dielectric over the tops of the chips. Interconnection in this approach is achieved by: forming via holes in the dielectric to the pads of the chips; subsequently metallizing the entire surface; and patterning the metal to form the interconnect. The HDI overlay approach distinguishes over the STD approach in that chips are placed on a substrate and subsequently a polymer overlay is adhered over the tops of the chips. This overlay bridges the gaps between the chips. Again interconnection is provided by forming via holes in the polymer dielectric, metallizing the entire surface of the overlay and pattering the metal to form the interconnect. A discussion of the HDI overlay approach is provided by Eichelberger et al. U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method," and U.S. Pat. No. 4,918,811, entitled "Multichip Integrated Circuit Packaging Method." The subject invention falls into the category of "circuit board above chips" and most closely resembles the STD approach.
Depending on the application and on the choice of multichip module technique, there are a series of problems associated with interconnect of electronic components which are solved with varying degrees of success. The rest of this section discusses these problems in terms of the solution provided by each of the basic prior art multichip module technologies. The problems discussed include heat removal, interconnect density, high frequency performance, alignment of chips or interconnect to the circuit board, reliability, ease of manufacture, interconnection to the next level, capability of repair, substrate choice and hermeticity.